This is gathered from various sources online, including the FDT of the device, the comments on the announcement, Jeff Gerling’s thread, and more. Updated further on September 29 and October 1st.
Pricing
$60 for the 4GB of RAM model and $80 for the 8GB of RAM one.
SoC
The SoC is on TSMC’s 16nm process. The memory configuration is a 32-bit wide LPDDR4X bus, with a peak bandwidth of 17GB/sec.
No video encoder onboard. For video decoding, only one codec is supported, HEVC. A new ISP, designed in-house by Raspberry Pi (PiSP) is rated at 1 gigapixel/sec, a very significant performance boost.
The CPU is a quad-core Cortex-A76 complex clocked at 2.4 GHz with a standard configuration that includes crypto extensions. As this is using a Cortex-A76, a core that only supports 32-bit code execution at EL0, Raspberry Pi 4 is the end of the road for bare metal RISC OS.
Each Cortex-A76 core has 64KB of L1I, 64KB of L1D and 512KB of L2. A 2MB shared L3 is present.
PCIe
2 PCIe controllers used on Raspberry Pi 5:
- PCIe x4: configured as Gen2, connection to the RP1 southbridge
- PCIe x1: configured as Gen2, overridable to Gen3. Exposed for external use.
An IOMMU is present but isn’t standard (bcm2712-iommu). The PCIe controller isn’t exposed as having coherent DMA.
GPU
The GPU operates at up to 1 GHz with support of 8 render targets, making going beyond OpenGL 2.1 possible. The virtual address size stays the same (32-bit).
In addition to that, the number of slices has been doubled with the design going from 8 to 16 QPUs. This results in a >2x performance boost.
The southbridge
RP1 (on TSMC 40nm) is connected over a PCIe 2.0 x4 link. It contains at least:
- PL011 serial ports (6 of them)
- 8 SPI controllers
- 7 I2C controllers
- 2 PWM
- 3 I2S
- 1 analog to digital converter
- GPIOs
- Cadence MACB Ethernet controller
- 2 CSI controllers
- 2 SDHCI controllers
- 1 DMA controller
- 2 Synopsys DWC3 USB controllers
- 2 DSI controllers
- 1 DPI controller
- Analog video output (VEC) – supports 3 channels (incl VGA) – although the RPi5 ships with composite only
And compute wise:
- 1 PIO block (w/ doubled FIFO depth)
- 2x Cortex-M3
The “special” bit: This is all exposed as a single PCIe device (1de4:0001). No separate devices exposed for each of those functions. This is unexpected from the standardisation point of view.
For ACPI-capable OSes, I’d recommend masking all of this away and not expose that PCIe bus at all (pre-initialise the controller and expose devices directly).
Performance
Compared to RK3588 (at 2.3 GHz on big cores) benchmarking the big core cluster only, Raspberry Pi 5 (at 2.4 GHz) is ~12% slower on single-core and 40% slower all-core on Geekbench 6. We can conclude that the memory subsystem is still far from ideal as those two are 4x Cortex-A76 platforms…
Note that the default Raspberry Pi 5 kernel on Raspbian uses 16KB pages. The generic Raspberry Pi kernel (kernel8) – which uses 4KB pages – also works.
On the storage side, we get SDR104 UHS-I support.
Boot process
No start.elf required, VideoCore firmware has been reduced to an (embedded)variant stored on a 2MB SPI flash. config.txt is parsed as usual.
There’s no ThreadX anymore. bootmain is a 508KB ELF binary that runs on the VideoCore, shipped in compressed form on the EEPROM. The interface between the VideoCore and the Arm is quite minimalistic and reduced compared to previous generations.
About standard boot firmware: well it’s a Raspberry Pi… and is not exactly compliant to what you’d usually expect so…
QoL features
- Real-time clock
- Power button
- Dedicated debug UART – doesn’t go through RP1