Arm CPUs with sequential consistency

(NVIDIA Xavier Series SoC Technical Reference Manual 1.4p, page 576)

One of the few general purpose processors in the wild with sequential consistency is the NVIDIA Carmel CPU core, present on the Tegra Xavier processor.

The 64-bit Tegra K1 (with Denver) also implements sequential consistency as the memory model. It also had a coherent instruction cache, a feature that was removed from Xavier. Meanwhile, Tegra X2 has 2 Denver2 cores implementing SC and 4 Cortex-A57s which don’t.

As such, Arm CPUs are available with memory models ranging from the weak one defined by the Arm ARM to sequential consistency. On Arm CPUs with SC, barriers during normal operation to coherent memory are analogous to NOPs.

The Fujitsu A64fx processor implements TSO as the memory model. Meanwhile, Apple processors can be switched to TSO through a write to ACTLR_EL1.

One of the uses for a stronger memory model on an Arm CPU is emulating other architectures with stronger memory ordering guarantees in a fast way… such as x86. Having support for a stronger memory model in hardware can decrease that overhead significantly.

Leave a comment

Your email address will not be published. Required fields are marked *